The present disclosure relates to a technique to enhance testability of semiconductor integrated circuits, and specifically to a technique to enhance testability of an asynchronous circuit including an asynchronous memory element such as a Muller's C-element, an asymmetric C-element, a latch, etc.
Along with miniaturization, increased scale, and reduced power consumption of semiconductor integrated circuits in recent years, the throughput of synchronous circuits has been approaching its limit due to variations in the amount of signal delay caused by fabrication variations, degradation in characteristics, a voltage fluctuation, etc., clock skew, the use of variable clocks, and the like. Thus, the use of asynchronous circuits has been reviewed. In the field of semiconductor integrated circuits, globally asynchronous locally synchronous (GALS) architecture which globally allows asynchronous operation and locally allows synchronous operation is expected to increase.
The asynchronous circuits can operate in a self-timing manner, and thus the asynchronous circuits are less susceptible to various types of signal delay. Moreover, the asynchronous circuits require no operation clock signal, and thus the asynchronous circuits consume no power in a stable state. On the other hand, the asynchronous circuits have to be designed in consideration of hazards and races, and in particular, testing the asynchronous circuits is more difficult than testing the synchronous circuits.
A scan method widely used for the synchronous circuits can be applied in enhancement of testability of the asynchronous circuits. That is, in the scan method, a test is performed in such a manner that a shift register (scan chain) for test is formed, a test pattern is scanned in the shift register, a response pattern of an asynchronous circuit to the test pattern is captured by the shift register, and the response pattern is scanned out.
In a synchronous circuit, at an input side of a flip-flop used as a memory element, a multiplexer configured to select one of an output of a flip-flop of a preceding stage or an output of the synchronous circuit is inserted, thereby easily forming a shift register. In contrast, the asynchronous circuit holds a value, not by a flip-flop, but by a Muller's C-element, etc. which holds a value by signal feedback inside the element, and thus a scan flip-flop for test use only has to be inserted in such a feedback path to form a shift register. Thus, enhancing the testability of the asynchronous circuits increases not only a circuit area overhead, but also a signal delay overhead.
Various methods have been proposed to reduce the circuit area and signal delay overheads associated with enhancing the testability of the asynchronous circuits. For example, the signal delay overhead is reduced by using level sensitive scan design (LSSD) single latch design in which a flip-flop includes an LSSD latch having an L1 latch (master latch) and an L2 latch (slave latch) which operate with different clock signals, and the L2 latch is disposed outside a feedback path. Moreover, the circuit area overhead is minimized by using so-called L1L2* single latch design in which a latch outside a feedback path of each of partial circuits is omitted, and latches of one partial circuit of a combinational circuit obtained by dividing the combinational circuit into two parts and latches of the other partial circuit are alternately connected to form LSSD latches (F. te Beest, A. Peeters, K. Van Berkel, and H. Kerkhoff, “Synchronous full-scan for asynchronous handshake circuits,” J. Electron. Test., vol. 19, no. 4, pp. 397-406, 2003).
Alternatively, in the L1L2* single latch design, only a multiplexer is left in the feedback path, and a latch is inserted in a scan path outside the feedback path, thereby minimizing the circuit area and signal delay overheads (International Patent Publication No. WO2006/013524). Moreover, there is a configuration in which independently operable latches are inserted in a feedback path and a scan path to allow a test pattern to be scanned in/out with an internal state of a memory element being maintained (International Patent Publication No. WO2010/001187).
As described above, when the scan method is applied in the enhancement of the testability of the asynchronous circuits, a shift register has to be added, which may increase the circuit area and signal delay overheads. When the L1L2* single latch design is used to solve the above discussed problem, application and observation of a given test pattern can no longer be ensured if there is input/output dependency between the L1 latch and the L2* latch which are paired as an LSSD latch. That is, in the L1L2* single latch design, the asynchronous circuits may not be completely tested. In particular, in the asynchronous circuit disclosed in International Patent Publication No. WO2006/013524, the latch is disposed outside the feedback path, and thus depending on a state of the multiplexer in performing scan in/out operation, the circuit may oscillate if a signal loop including only one latch is formed in the asynchronous circuit.
Moreover, in any of the conventional methods, a test pattern is not stored in an asynchronous memory element which is initially included in the asynchronous circuit, but a test pattern and a response pattern of the asynchronous circuit are stored by a flip-flop or a latch which is additionally inserted. Thus, only scanning in the test pattern and scanning out the response pattern cannot test an asynchronous memory element such as a Muller's C-element. That is, the asynchronous memory element is incompletely tested.
Thus, there is a need for an improved asynchronous memory element (hereinafter referred to as “scan asynchronous memory element”) suitable for enhancement of testability of asynchronous circuits. Moreover, there are needs for a semiconductor integrated circuit which includes such a scan asynchronous memory element and has design for enhanced testability, a method for designing such a semiconductor integrated circuit, and a method for generating a test pattern for such a semiconductor integrated circuit.